Methods for etching a dielectric barrier layer with high selectivity

ABSTRACT

Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in a reactor, flowing a gas mixture containing H 2  gas, fluorine containing gas, at least an insert gas into the reactor, and etching the exposed portion of the dielectric barrier layer selectively to the dielectric bulk insulating layer.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.11,388,246, filed Mar. 22, 2006, which is incorporated by reference inits entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor processingtechnologies and, more specifically, to a method for etching adielectric barrier layer with high selectivity to a dielectric bulkinsulating layer in semiconductor processing.

2. Description of the Related Art

Integrated circuits have evolved into complex devices that can includemillions of components (e.g., transistors, capacitors and resistors) ona single chip. The evolution of chip designs continually requires fastercircuitry and greater circuit density. The demands for greater circuitdensity necessitate a reduction in the dimensions of the integratedcircuit components.

As the dimensions of the integrated circuit components are reduced (e.g.sub-micron dimensions), the materials used to fabricate such componentscontribute to their electrical performance. For example, metalinterconnects with low resistance (e.g., copper and aluminum) provideconductive paths between the components on integrated circuits.

Typically, the metal interconnects are electrically isolated from eachother by a dielectric bulk insulating material. When the distancebetween adjacent metal interconnects and/or the thickness of thedielectric bulk insulating material has sub-micron dimensions,capacitive coupling potentially occurs between such interconnects.Capacitive coupling between adjacent metal interconnects may cause crosstalk and/or resistance-capacitance (RC) delay which degrades the overallperformance of the integrated circuit.

In order to minimize capacitive coupling between adjacent metalinterconnects, low dielectric constant bulk insulating materials (e.g.,dielectric constants less than about 4.0) are needed. Examples of lowdielectric constant bulk insulating materials include silicon dioxide(SiO₂), silicate glass, fluorosilicate glass (FSG), and carbon dopedsilicon oxide (SiOC), among others.

In addition, a dielectric barrier layer often separates the metalinterconnects from the dielectric bulk insulating materials. Thedielectric barrier layer minimizes the diffusion of the metal into thedielectric bulk insulating material. Diffusion of the metal into thedielectric bulk insulating material is undesirable because suchdiffusion can affect the electrical performance of the integratedcircuit, or render it inoperative. The dielectric layer needs to have alow dielectric constant in order to maintain the low-k characteristic ofthe dielectric stack between conductive lines. The dielectric barrierlayer also acts as an etch-stop layer for a dielectric bulk insulatinglayer etching process, so that the underlying metal will not be exposedto the etching environment. The dielectric barrier layer has adielectric constant of about 5.5 or less. Examples of dielectric barrierlayer are silicon carbide (SiC) and nitrogen containing silicon carbide(SiCN), among others.

Some integrated circuit components include multilevel interconnectstructures (e.g., dual damascene structures). Multilevel interconnectstructures can have two or more bulk insulating layers, low dielectricbarrier layers, and metal layers stacked on top of one another. As anexemplary dual damascene structure shown in FIG. 1A, a dielectric bulkinsulating layer 108 with an underlying dielectric barrier layer 106 arestacked on another previously formed interconnect with a conductivelayer 104 embedded in another dielectric bulk insulating layer 102. As avia/trench etching process is completed and a via/trench 110 is definedon the dielectric bulk insulating layer 108, the exposed dielectricbarrier layer 106 defined by the via/trench 110 is subsequently removedto expose the underlying conductive layer 104 so that the followingdeposited conductive layer 116 can be connected and jointedtherethrough, as shown in FIG. 1B. However, the similarity of theselected materials of the bulk insulating layer 108 and dielectricbarrier layer 106 results in similar etch properties therebetween,thereby causing poor selectivity during etching. As shown in FIG. 1C, asthe dielectric barrier layer 106 is etched, the dielectric bulkinsulating layer 108 may be attacked simultaneously by the reactiveetchant species, resulting in non-uniformity or tapered profile on thetop and/or sidewall of the layer 114. In embodiments where theunderlying conductive layer 104 is not aligned with the trench opening110, as shown in FIG. 1D, the underlying dielectric bulk insulatinglayer 102 may be attacked 112 during etching of the dielectric barrierlayer 106 due to poor selectivity to the dielectric bulk insulatinglayer 102.

Therefore, there is a need for a method of etching a dielectric barrierlayer with high selectivity to a dielectric bulk insulating layer.

SUMMARY OF THE INVENTION

Methods for etching a dielectric barrier layer with high selectivity toa dielectric bulk insulating layer are provided in the presentinvention. In one embodiment, a method for etching a dielectric barrierlayer includes providing a substrate having a portion of a dielectricbarrier layer exposed through a dielectric bulk insulating layer in areactor, flowing a gas mixture containing H₂ gas into the reactor, andetching the exposed portion of the dielectric barrier layer selectivelyto the dielectric bulk insulating layer.

In another embodiment, a method for etching a dielectric barrier layerincludes providing a substrate having a portion of a dielectric barrierlayer exposed therethrough a dielectric bulk insulating layer in areactor, flowing a gas mixture containing H₂ gas and a fluorinecontaining gas into the reactor, and etching the exposed portion of thedielectric barrier layer in a presence of a plasma formed from the gasmixture.

In yet another embodiment, a method for etching a dielectric barrierlayer includes providing a substrate having a portion of a dielectricbarrier layer exposed through a dielectric bulk insulating layer in areactor, wherein the dielectric barrier layer is a carbon containingsilicon film, flowing a gas mixture containing H₂ gas, a fluorinecontaining gas and at least one insert gas into the reactor, and etchingthe exposed portion of the dielectric layer selectively to thedielectric bulk insulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentinvention are attained and can be understood in detail, a moreparticular description of the invention, briefly summarized above, maybe had by reference to the embodiments thereof which are illustrated inthe appended drawings.

FIGS. 1A-1D are sectional views of exemplary interconnect structures;

FIG. 2 is a schematic cross-sectional view of a plasma reactor usedaccording to one embodiment of the invention;

FIG. 3 is a flow diagram of one embodiment of a dielectric barrier layerremoval process on an interconnect structure according to one embodimentof the invention; and

FIGS. 4A-4B are sectional views of one embodiment of an interconnectstructure having an exposed dielectric barrier layer disposed on asubstrate.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements and features of oneembodiment may be beneficially incorporated in other embodiments withoutfurther recitation.

It is to be noted, however, that the appended drawings illustrate onlyexemplary embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

DETAILED DESCRIPTION

Embodiments of the present invention include methods for etching adielectric barrier layer with high selectivity to a dielectric bulkinsulating layer. The methods preserve the profile and dimension of thefeatures formed on a substrate with selectively etching the dielectricbarrier layer substantially without attacking the adjacent dielectricbulk insulating layer and/or underlying conductive layer and dielectricbulk insulating layer. The high etching selectivity is achieved by usinga gas mixture containing hydrogen gas (H₂) to etch the dielectricbarrier layer.

FIG. 2 depicts a schematic, cross-sectional diagram of one embodiment ofa plasma source etch reactor 202 suitable for performing the dielectricbarrier layer etch according to the present invention. One such etchreactor suitable for performing the invention is the ENABLER® processingchamber, available from Applied Materials, Inc., of Santa Clara, Calif.It is contemplated that the dielectric barrier layer etching processdescribed herein may be performed in other etch reactors, includingthose from other manufacturers.

In one embodiment, the reactor 202 includes a process chamber 210 havinga conductive chamber wall 230. The temperature of the chamber wall 230is controlled using liquid-containing conduits (not shown) that arelocated in and/or around the wall 230.

The chamber 210 is a high vacuum vessel that is coupled through athrottle valve 227 to a vacuum pump 236. The chamber wall 230 isconnected to an electrical ground 234. A liner 231 is disposed in thechamber 210 to cover the interior surfaces of the walls 230. The liner231 facilitates in-situ self-cleaning capabilities of the chamber 210,so that byproducts and residues deposited on the liner 231 can bereadily removed from the liner 231.

The process chamber 210 also includes a support pedestal 216 and ashowerhead 232. The support pedestal 216 is disposed below theshowerhead 232 in a spaced-apart relation. The support pedestal 216 mayinclude an electrostatic chuck 226 for retaining a substrate 200 duringprocessing. Power to the electrostatic chuck 226 is controlled by a DCpower supply 220.

The support pedestal 216 is coupled to a radio frequency (RF) bias powersource 222 through a matching network 224. The bias power source 222 isgenerally capable of producing an RF signal having a tunable frequencyof from about 50 kHz to about 60 MHz and a bias power of about 0 to5,000 Watts. Optionally, the bias power source 222 may be a DC or pulsedDC source.

The temperature of the substrate 200 supported on the support pedestal216 is at least partially controlled by regulating the temperature ofthe support pedestal 216. In one embodiment, the support pedestal 216includes a cooling plate (not shown) having channels formed therein forflowing a coolant. In addition, a backside gas, such as helium (He) gas,provided from a gas source 248, fits provided into channels disposedbetween the back side of the substrate 200 and grooves (not shown)formed in the surface of the electrostatic chuck 226. The backside Hegas provides efficient heat transfer between the pedestal 216 and thesubstrate 200. The electrostatic chuck 226 may also include a resistiveheater (not shown) within the chuck body to heat the chuck 226 duringprocessing. In one embodiment, the substrate 200 is maintained at atemperature of between about 10 to about 500 degrees Celsius.

The showerhead 232 is mounted to a lid 213 of the processing chamber210. A gas panel 238 is fluidly coupled to a plenum (not shown) definedbetween the showerhead 232 and the lid 213. The showerhead 232 includesa plurality of holes to allow gases provided to the plenum from the gaspanel 238 to enter the process chamber 210. The holes in the showerhead232 may be arranged in different zones such that various gases can bereleased into the chamber 210 with different volumetric flow rates.

The showerhead 232 and/or an upper electrode 228 positioned proximatethereto is coupled to an RF source power 218 through an impedancetransformer 219 (e.g., a quarter wavelength matching stub). The RFsource power 218 is generally capable of producing an RF signal having atunable frequency of about 160 MHz and a source power of about 0 to5,000 Watts.

The reactor 202 may also include one or more coil segments or magnets212 positioned exterior to the chamber wall 230, near the chamber lid213. Power to the coil segment(s) 212 is controlled by a DC power sourceor a low-frequency AC power source 254.

During substrate processing, gas pressure within the interior of thechamber 210 is controlled using the gas panel 238 and the throttle valve227. In one embodiment, the gas pressure within the interior of thechamber 210 is maintained at about 0.1 to 999 mTorr.

A controller 240, including a central processing unit (CPU) 244, amemory 242, and support circuits 246, is coupled to the variouscomponents of the reactor 202 to facilitate control of the processes ofthe present invention. The memory 242 can be any computer-readablemedium, such as random access memory (RAM), read only memory (ROM),floppy disk, hard disk, or any other form of digital storage, local orremote to the reactor 202 or CPU 244. The support circuits 246 arecoupled to the CPU 244 for supporting the CPU 244 in a conventionalmanner. These circuits include cache, power supplies, clock circuits,input/output circuitry and subsystems, and the like. A software routineor a series of program instructions stored in the memory 242, whenexecuted by the CPU 244, causes the reactor 202 to perform an etchprocess of the present invention.

FIG. 2 only shows one exemplary configuration of various types of plasmareactors that can be used to practice the invention. For example,different types of source power and bias power can be coupled into theplasma chamber using different coupling mechanisms. Using both thesource power and the bias power allows independent control of a plasmadensity and a bias voltage of the substrate with respect to the plasma.In some applications, the source power may not be needed and the plasmais maintained solely by the bias power. The plasma density can beenhanced by a magnetic field applied to the vacuum chamber usingelectromagnets driven with a low frequency (e.g., 0.1-0.5 Hertz) ACcurrent source or a DC source. In other applications, the plasma may begenerated in a different chamber from the one in which the substrate islocated, e.g., remote plasma source, and the plasma subsequently guidedinto the chamber using techniques known in the art.

FIG. 3 illustrates a flow diagram of one embodiment of a dielectricbarrier layer removal process 300 according to one embodiment of theinvention. FIGS. 4A-4B are schematic cross-sectional views illustratingthe sequence of the dielectric barrier layer removal process 300. Theprocess 300 may be stored in memory 242 as instructions that executed bythe controller 240 to cause the process 300 to be performed in thereactor 202.

The process 300 begins at step 302 by providing a substrate 400 having adielectric barrier layer in an interconnect structure in the reactor202. A dielectric stack 412, as shown in FIG. 4A, is disposed on a layer402 having at least one conductive layer 404, such as copper line,disposed therein. The dielectric stack 412 includes a dielectric bulkinsulating layer 408 over a dielectric barrier layer 406. A trench/via410 is formed in the dielectric bulk insulating layer 408 by aconventional etching process, such as dual damascene etching process. Inone embodiment, the dielectric bulk insulating layer 408 is a dielectricmaterial having a dielectric constant less than 4.0 (low-k materials).Examples of suitable materials include carbon-containing silicon oxides(SiOC), such as BLACK DIAMOND® dielectric material available fromApplied Materials, Inc., and other low-k polymers, such as polyamides.

The dielectric barrier layer 406 has a dielectric constant of about 5.5or less. In one embodiment, the dielectric barrier layer 406 is a carboncontaining silicon layer (SiC), a nitrogen doped carbon containingsilicon layer (SiCN), or the like. In the embodiment depicted in FIG.4A, the dielectric barrier layer is a SiCN film. An example of thedielectric barrier layer material is BLOK® dielectric material,available from Applied Materials, Inc.

In the embodiment depicted in FIG. 4A, the dielectric stack 410 isetched through an opening, thereby defining a feature 410, such as atrench or via, in the dielectric bulk insulating layer 408 over thedielectric barrier layer 406. A portion of the dielectric bulkinsulating layer 408 is removed to expose a surface 414 of thedielectric barrier layer 406. A conductive layer 404 present in thelayer 402 is below the feature 410 formed in the dielectric barrierlayer 406. In one embodiment, the dielectric bulk insulating layer 408is etched using a plasma formed from fluorine and carbon. The dielectricbulk insulating layer 408 may be etched in an etch chamber, such as thereactor 202 described in FIG. 2 or other suitable reactor.

In one embodiment, the etch process may be performed by supplying carbonand fluorine containing gas, such as carbon tetrafluoride (CF₄), atbetween about 5 to about 250 sccm, applying a power between about 50Watt to about 2000 Watt, maintaining a temperature between about 0degrees Celsius to about 50 Celsius, and controlling process pressurebetween about 5 mTorr to about 200 mTorr into the reactor. In anotherembodiment, at least a carrier gas, such as argon (Ar), may also besupplied accompanying with the carbon and fluorine containing gas intothe reactor. The carrier gas may be supplied between about 50 to about500 sccm.

At step 304, a gas mixture containing H₂ gas is supplied into thereactor 202 to etch the exposed dielectric barrier layer 406 defined bythe features 410 formed in the dielectric bulk insulating layer 408. TheH₂ gas accompanying the gas mixture promotes etching of the dielectricbarrier layer 406 by generating free hydrogen radicals that react withthe nitrogen and carbon components of the dielectric barrier layer 406,thereby selectively decomposing the dielectric barrier layer 406substantially without etching the dielectric bulk insulating layer 408.In one embodiment, the gas mixture may include, but is not limited to,H₂ gas and a fluorine containing gas. Suitable examples of fluorinecontaining gas may include, but not limited to, CH₂F₂, CHF₃, CH₃F, C₂F₆,CF₄, C₃F₈, C₄F₆, C₄F₈, and the like. In another embodiment, the gasmixture may include H₂ gas, a fluorine containing gas and at least oneinsert gas. The insert gas may be selected from a group consisting ofargon gas (Ar), helium gas (He), nitric oxide (NO), carbon monoxide(CO), nitrous oxide (N₂O), oxygen gas (O₂), nitrogen gas (N₂) and thelike. In embodiments preventing the underlying conductive layer 404 fromoxidizing during the etching process, the gas mixture does not includeany gases containing oxygen.

Several process parameters are regulated at step 304 while the gasmixture is supplied into the etch reactor. In one embodiment, a pressureof the gas mixture in the etch reactor is regulated between about 10mTorr to about 200 mTorr, for example, between about 20 mTorr to about60 mTorr, and the substrate temperature is maintained between about 0degrees Celsius and about 50 degrees Celsius, for example, between about0 degrees Celsius and about 25 degrees Celsius.

At step 306, a plasma is formed from the gas mixture to etch the exposeddielectric barrier layer 406 and remove the dielectric barrier layer 406from above the conductive layer 402 defined by the trench 410 in thedielectric bulk insulating layer 408 on the substrate, as shown in FIG.4B. In one embodiment, RF source power may be applied at a power ofabout 100 Watts to about 800 Watts to provide a plasma from the gasmixture. The H₂ gas may be provided at a flow rate between about 5 sccmto about 100 sccm, for example, about between about 20 sccm to about 60sccm. The fluorine containing gas, such as CH₂F₂, may be provided at aflow rate at a rate between about 0 sccm to about 80 sccm, for example,between about 10 sccm to about 30 sccm. The insert gas, such as Ar or O₂gas, may be provided at a flow rate between about 50 sccm to about 500sccm, for example about 100 sccm to about 200 sccm. The etching time maybe processed at between about 10 seconds to about 80 seconds.

The etching process with the H₂ gas containing gas mixture enables thedielectric barrier layer 406 to be selectively etched in a mannerwithout attacking the adjacent and/or underlying dielectric bulkinsulating layer 408. The etching gas mixture of etching dielectricbarrier layer 406 creates a high selectivity to dielectric bulkinsulating layer 408 by generating hydrogen free radicals that mostlyreact with the nitrogen and carbon bonds contained in the dielectricbarrier layer 406, thereby allowing the exposed dielectric barrier layer406 defined by the trenches 410 to be uniformly etched. In oneembodiment, the selectivity of the dielectric barrier layer 406 to bulkinsulating layer 408 is at least 5, for example, 15.

The process of etching the dielectric barrier layer 406 is terminatedafter reaching an endpoint signaling that the underlying conductivelayer 404 has been exposed. The endpoint may be determined by anysuitable method. For example, the endpoint may be determined bymonitoring optical emissions, expiration of a predefined time period orby another indicator for determining that the dielectric barrier layer406 to be etched has been sufficiently removed.

Thus, the present invention provides an improved method for etching adielectric barrier layer with high selectivity to a dielectric bulkinsulating layer. The method advantageously facilitates the profile anddimension of the features in an interconnect structure by selectivelyetching the dielectric barrier layer defined by the trenches indielectric bulk insulating layer.

While the foregoing is directed to embodiments of the present invention,other and further embodiments of the invention may be devised withoutdeparting from the basic scope thereof, and the scope thereof isdetermined by the claims that follow.

1. A method for etching a dielectric barrier layer in an interconnectstructure, comprising: providing a substrate having a portion of adielectric barrier layer having a dielectric constant less than 5.5exposed through a dielectric bulk insulating layer in a reactor; forminga plasma from a gas mixture containing at least H₂ gas in the reactor;and etching the exposed portion of the dielectric barrier layerselectively to the dielectric bulk insulating layer with the plasmaformed in the reactor, wherein the selectivity is at least
 5. 2. Themethod of claim 1, wherein the gas mixture from which the plasma isformed further comprises: a fluorine containing gas.
 3. The method ofclaim 1, wherein the gas mixture from which the plasma is formed furthercomprises: at least one insert gas.
 4. The method of claim 1, whereinthe dielectric barrier layer selectively to the dielectric bulkinsulating layer is
 15. 5. The method of claim 1, wherein the step ofetching further comprises: maintaining a process pressure at betweenabout 10 mTorr to about 200 mTorr; controlling substrate temperaturebetween about 0 degrees Celsius to about 50 degrees Celsius; andapplying a plasma power between about 100 Watts to about 800 Watts. 6.The method of claim 2, wherein the fluorine containing gas is at leastone of CH₂F₂, CHF₃, CH₃F, C₂F₆, CF₄ or C₃F₈.
 7. The method of claim 3,wherein the insert gas is at least one of Ar, O₂, CO, NO, N₂O, He or N₂.8. The method of claim 1, wherein the dielectric insulating layer has adielectric constant less then
 4. 9. The method of claim 1, wherein thedielectric layer is a carbon containing silicon film.
 10. The method ofclaim 1, further comprising: removing the exposed dielectric barrierlayer; and exposing an underlying conductive layer disposed below thedielectric barrier layer on the substrate.
 11. A method for etching adielectric barrier layer in an interconnect structure, comprising:providing a substrate having a portion of a dielectric barrier layerhaving a dielectric constant less than 5.5 exposed through a dielectricbulk insulating layer having a dielectric constant less then 4 in areactor; flowing a gas mixture containing H₂ gas and a fluorinecontaining gas into the reactor; etching the exposed portion of thedielectric barrier layer in a presence of a plasma formed from the gasmixture; and exposing an underlying conductive layer disposed below thedielectric barrier layer on the substrate.
 12. The method of claim 11,wherein the fluorine containing gas is at least one of CH₂F₂, CHF₃,CH₃F, C₂F₆, CF₄ and C₃F₈.
 13. The method of claim 12, wherein the gasmixture further comprises: an insert gas selected from a groupconsisting of Ar, O₂, CO, NO, N₂O, He and N₂.
 14. The method of claim11, wherein the step of flowing a gas mixture further comprises:maintaining a process pressure at between about 10 mTorr to about 200mTorr; controlling substrate temperature between about 0 degree Celsiusto about 50 degree Celsius; and applying a plasma at between about 100Watts to about 800 Watts.
 15. The method of claim 11, wherein thedielectric barrier layer is a carbon containing silicon film.
 16. Amethod for etching a dielectric barrier layer in an interconnectstructure, comprising: providing a substrate having a portion of adielectric barrier layer exposed through a dielectric bulk insulatinglayer having a dielectric constant less then 4 in a reactor, wherein thedielectric barrier layer is a carbon containing silicon film; flowing agas mixture containing H₂ gas and a fluorine containing gas into thereactor; and forming a plasma from the gas mixture in the reactor; andetching the exposed portion of the dielectric barrier layer selectivelyto the dielectric bulk insulating layer with the plasma formed in thereactor, wherein the selectivity is at least
 5. 17. The method of claim16, wherein the step of flowing a gas mixture further comprises: flowingthe H₂ gas at a flow rate between about 5 sccm to about 100 sccm;flowing the fluorine containing gas at a rate between about 0 sccm toabout 80 sccm, wherein the fluorine containing gas is selected from agroup consisting of CH₂F₂, CHF₃, CH₃F, C₂F₆, CF₄ and C₃F₈; and flowingthe insert gas at a flow rate between about 50 sccm to 500 sccm, whereinthe insert gas is selected from a group consisting Ar, O₂, CO, NO, N₂O,He and N₂.
 18. The method of claim 16, wherein the step of flowing thegas mixture further comprises: maintaining a process pressure at betweenabout 10 mTorr to about 200 mTorr; controlling substrate temperaturebetween about 0 degrees Celsius to about 50 degrees Celsius; andapplying a plasma at between about 100 Watts to about 800 Watts.